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[ak4611] ms1050-e-02 2010/06 - 1 - general description the ak4611 is a single chip audio codec that in cludes four adc channels and eight dac channels. the converters are designed with e nhanced dual bit architecture for the adc?s, and advanced multi-bit architecture for the dac, enabling very low noise per formance. fabricated on a low power process, the ak4611 operates off of a +3.3v analog supply and a +1.8v digital supply. the ak4611 supports both single-ended and differential inputs and outputs. a wide range of applications can be realized, including home theater, pro audio and car audio. the ak4611 is available in an 80-pin lqfp package. features 1. 4channel 24bit adc - 128x oversampling - linear phase digital anti-alias filter - analog anti-alias filter for single -ended input and differential input - adc s/(n+d) 92db: single-ended input 97db: differential input - adc dr, s/n 103db: single-ended input 104db: differential input - digital hpf for offset cancellation - i/f format: msb justified, i 2 s or tdm - overflow flag 2. 8channel 24bit dac - 128x oversampling - linear phase 24bit 8 times digital filter - analog smoothing filter for single-ended output - dac s/(n+d) 94db: single-ended output 100db: differential output - dac dr, s/n 105db: single-ended output 108db: differential output - individual channel digital volume with 256 levels and 0.5db steps - soft mute - de-emphasis for 32khz, 44.1khz and 48khz - zero detect function - i/f format: msb justified, lsb justified (16bit, 20bit, 24bit), i 2 s or tdm 3. sampling frequency - normal speed mode: 32khz to 48khz - double speed mode: 64khz to 96khz - quad speed mode: 128khz to 192khz 4. master / slave mode ak4611 4/8-channel audio codec
[ak4611] ms1050-e-02 2010/06 - 2 - 5. master clock - slave mode: 256fs, 384fs or 512fs (normal speed mode: fs=32khz 48khz) 256fs (double speed mode: fs=64khz 96khz) 128fs (quad speed mode: fs=128khz 192khz) - master mode: 256fs or 512fs (normal speed mode: fs=32khz 48khz) 256fs (double speed mode: fs=64khz 96khz) 128fs (quad speed mode: fs=128khz 192khz) 6. 4-wire serial and i 2 c bus p i/f for mode setting 7. power supply - analog power supply: avdd1, avdd2 = 3.0 3.6v - digital power supply: dvdd = 1.6 2.0v - i/o buffer power supply: tvdd1, tvdd2 = 1.6 3.6v 8. power supply current : 81 ma (fs=48khz) 9. ta = -20 ~ 85 o c (ak4611eq), - 40 105 o c (AK4611VQ) 10. package: 80pin lqfp (0.5mm pitch)
[ak4611] ms1050-e-02 2010/06 - 3 - block diagram audio i/f scf1 lout1+ / lout1 dac1 datt1 dem1 lrck bick sdti1 sdti2 sdti3 mclk lrck bick sdout1 sdin1 sdin2 sdin3 sdto1 sdti4 sdin4 dac1 datt1 dem1 dac2 datt2 dem2 dac2 datt2 dem2 dac3 datt3 dem3 dac3 datt3 dem3 dac4 datt4 dem4 dac4 datt4 dem4 lout1- adc2 hpf2 adc2 hpf2 adc1 hpf1 adc1 hpf1 lin1+ / lin1 lin 1- sdout2 tst7 tst8 sdto2 tst6 up i/f i2c csn cclk / scl cdti / sda cdto cad1 cad0 mcko xto xti / mcki divider x?tal oscillation rin1+ / rin1 rin1- lin2+ / lin2 lin2- rin2+ / rin2 rin2- scf1 rout1+ / rout1 rout1- scf2 lout2+ / lout2 lout2- scf2 rout2+ / rout2 rout2- scf3 lout3+ / lout3 lout3- scf3 rout3- scf4 lout4+ / lout4 lout4- scf4 rout4+ / rout4 rout4- pdn m/s tst2 tst1 tst4 tst3 ovf1 / dzf1 ovf2 / dzf2 vcom a vdd1 vrefh1 vrefh2 vss1 a vdd2 vss2 dvdd vss3 tvdd1 vss4 tvdd2 tst5 dvmpd rout3+ / rout3 figure 1. block diagram
[ak4611] ms1050-e-02 2010/06 - 4 - ordering guide ak4611eq -20 a +85 q c 80pin lqfp (0.5mm pitch) AK4611VQ -40 a +105 q c 80pin lqfp (0.5mm pitch) akd4611 evaluation board for ak4611 pin layout (top view) 80 p in lqf p lout4+ / lout4 lout2+ / lout2 61 62 63 64 65 66 67 68 69 70 72 73 71 74 76 77 75 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 29 28 30 27 25 24 26 23 22 21 60 59 58 5 7 56 5 5 54 5 3 52 51 50 49 48 47 46 45 44 43 42 41 lout2- rout2+ / rout2 rout2- lout3+ / lout3 lout3- rout3+ / rout3 rout3- vss2 a vdd2 vrefh2 lout4- rout4+ / rout4 rout4- tst9 tst10 tst11 ts t12 tst13 tst14 1 rout1- rout1+ / rout1 tst4 tst5 cad0 lout1+ / lout1 dvmpd lout1- tst8 tst7 i2c cclk / scl cdti / sda cdto tst1 tst3 nc xto cad1 csn tvdd2 vss3 dvdd mcko m/s tst2 pdn sdti 4 sdti 3 sdti 2 bi ck lrck sdti 1 tst6 sdto2 sdto1 vss4 tvdd1 xti / mcki tst1 5 tst1 6 ovf1 / dzf1 lin1- rin1+ / rin1 rin1- lin2+ / lin2 lin2- rin2+ / rin2 tst1 7 tst1 8 rin2- vss1 vrefh1 vcom tst1 9 tst2 0 ovf2 / dzf2 lin1+ / lin1 avdd1 figure 2. pin layout
[ak4611] ms1050-e-02 2010/06 - 5 - compatibility with ak4628 1. functions function ak4628 ak4611 number of adc channel 2-channel 4-channel number of dac channel 8-channel 8-channel input single single or diff output single single or diff i/f format i2s, lj, rj(20/24bit), tdm i2s, lj, rj(16/20/24bit), tdm tdm512 no fs=48khz xtal osc no yes parallel / serial select pin yes no control data output pin no yes ta -40 a +85 q c -40 a +105 q c package 44pinlqfp 80pinlqfp 2. power supply voltage name ak4628 ak4611 avdd 4.5 a 5.5v no avdd1 no 3.0 a 3.6v avdd2 no 3.0 a 3.6v dvdd 4.5 a 5.5v 1.6 a 2.0v tvdd 2.7 a 5.5v no tvdd1 no 1.6 a 3.6v tvdd2 no 1.6 a 3.6v 3. specification parameter ak4628 ak4611 fs (ad/da) 96k / 192k 192k / 192k thd+n (ad/da) si ngle: 92 / 90 differential : - / - single: 92 / 94 differential : 97 / 100 s/n (ad/da) single: 102 / 106 differential : - / - single: 103 / 105 differential: 104 / 108 output datt 128 level 256 level p i/f 100k i2c, 3wire 400k i2c, 4wire
[ak4611] ms1050-e-02 2010/06 - 6 - pin/function no. pin name i/o function 1 tst1 i test pin this pin must be connected to vss4. 2 tst3 i test pin this pin must be connected to tvdd2. 3 tst4 i test pin this pin must be connected to vss4. 4 tst5 i test pin this pin must be connected to vss4. 5 cad0 i chip address 0 pin 6 cad1 i chip address 1 pin 7 i2c i p i/f mode select pin ?l?: 4-wire serial, ?h?: i 2 c bus cclk i control data clock pin in serial control mode i2c = ?l?: cclk (4-wire serial) 8 scl i control data clock pin in serial control mode i2c = ?h?: scl (i 2 c bus) 9 csn i chip select pin in 4-wire serial control mode this pin must be connected to tvdd2 at i 2 c bus control mode cdti i control data input pin in serial control mode i2c = ?l?: cdti (4-wire serial) 10 sda i/o control data input pin in serial control mode i2c = ?h?: sda (i 2 c bus) 11 cdto o control data output pin in 4-wire serial control mode 12 tvdd2 - input / output buffer power supply 1 pin, 1.6v 3.6v 13 vss3 ground pin, 0v 14 dvdd - digital power supply pin, 1.6v 2.0v 15 nc - no connection. no internal bonding. this pin must be connected to the ground. 16 tst2 i test pin this pin must be connected to vss4. 17 m/s i master mode select pin ?l?: slave mode ?h?: master mode 18 mcko o master clock output pin 19 pdn i power-down & reset pin when ?l?, the ak4611 is powered-down and the control registers are reset to default state. if the state of cad1-0 changes, then the ak4611 must be reset by pdn. 20 xto o x?tal output pin xti i x?tal input pin 21 mcki i external master clock input pin 22 tvdd1 - input / output buffer power supply 1 pin, 1.6v 3.6v 23 vss4 - digital ground pin, 0v 24 sdto1 o audio serial data output 1 pin 25 sdto2 o audio serial data output 2 pin 26 tst6 o test pin this pin must be open. 27 lrck i/o input /output channel clock pin 28 bick i/o audio serial data clock pin 29 sdti1 i audio serial data input 1 pin 30 sdti2 i audio serial data input 2 pin 31 sdti3 i audio serial data input 3 pin 32 sdti4 i audio serial data input 4 pin 33 tst7 i test pin this pin must be connected to vss4.
[ak4611] ms1050-e-02 2010/06 - 7 - no. pin name i/o function 34 tst8 i test pin this pin must be connected to vss4. 35 dvmpd i dac output vcom voltage power down pin ?l?: dac outputs are vcom voltage ?h?: dac outputs are hi-z. lout1+ o lch analog positive output 1 pin (doe1 bit = ?h?) 36 lout1 o lch analog output 1 pin (doe1 bit = ?l?) 37 lout1- o lch analog negative output 1 pin (when doe1 bit = ?l?, this pin must be open.) rout1+ o rch analog positive output 1 pin (doe1 bit = ?h?) 38 rout1 o rch analog output 1 pin (doe1 bit = ?l?) 39 rout1- o rch analog negative output 1 pin (when doe1 bit = ?l?, this pin must be open.) lout2+ o lch analog positive output 2 pin (doe2 bit = ?h?) 40 lout2 o lch analog output 2 pin (doe2 bit = ?l?) 41 lout2- o lch analog negative output 2 pin (when doe2 bit = ?l?, this pin must be open.) rout2+ o rch analog positive output 2 pin (doe2 bit = ?h?) 42 rout2 o rch analog output 2 pin (doe2 bit = ?l?) 43 rout2- o rch analog negative output 2 pin (when doe2 bit = ?l?, this pin must be open.) lout3+ o lch analog positive output 3 pin (doe3 bit = ?h?) 44 lout3 o lch analog output 3 pin (doe3 bit = ?l?) 45 lout3- o lch analog negative output 3 pin (when doe3 bit = ?l?, this pin must be open.) rout3+ o rch analog positive output 3 pin (doe3 bit = ?h?) 46 rout3 o rch analog output 3 pin (doe3 bit = ?l?) 47 rout3- o rch analog negative output 3 pin (when doe3 bit = ?l?, this pin must be open.) 48 vss2 - ground pin, 0v 49 avdd2 - analog power supply pin, 3.0v 3.6v 50 vrefh2 i positive voltage reference input pin, avdd2 lout4+ o lch analog positive output 4 pin (doe4 bit = ?h?) 51 lout4 o lch analog output 4 pin (doe4 bit = ?l?) 52 lout4- o lch analog negative output 4 pin (when doe4 bit = ?l?, this pin must be open.) rout4+ o rch analog positive output 4 pin (doe4 bit = ?h?) 53 rout4 o rch analog output 4 pin (doe4 bit = ?l?) 54 rout4- o rch analog negative output 4 pin (when doe4 bit = ?l?, this pin must be open.) 55 tst9 o test pin this pin must be open. 56 tst10 o test pin this pin must be open. 57 tst11 o test pin this pin must be open. 58 tst12 o test pin this pin must be open. 59 tst13 o test pin this pin must be open. 60 tst14 o test pin this pin must be open. 61 tst15 o test pin this pin must be open. 62 tst16 o test pin this pin must be open. ovf1 o analog input overflow detect 1 pin ( note 1 ) this pin goes to ?h? if the analog input of lch or rch overflows. 63 dzf1 o zero input detect 1 pin ( note 2 ) when the input data of the group 1 follow total 8192 lrck cycles with ?0? input data, this pin goes to ?h?. and when rstn bit is ?0 ?, pmdac bit is ?0?, this pin goes to ?h?.
[ak4611] ms1050-e-02 2010/06 - 8 - no. pin name i/o function ovf2 o analog input overflow detect 2 pin ( note 1 ) this pin goes to ?h? if the analog input of lch or rch overflows. 64 dzf2 o zero input detect 2 pin ( note 2 ) when the input data of the group 2 follow total 8192 lrck cycles with ?0? input data, this pin goes to ?h?. and when rstn bit is ?0?, pmdac bit is ?0?, this pin goes to ?h?. lin1+ i lch analog positive i nput 1 pin (die1 bit = ?h?) 65 lin1 i lch analog input 1 pin (die1 bit = ?l?) 66 lin1- - lch analog negative input 1 pin (when die1 bit = ?l?, this pin must be open.) ( note 3 ) rin1+ i rch analog positive i nput 1 pin (die1 bit = ?h?) 67 rin1 i rch analog input 1 pin (die1 bit = ?l?) 68 rin1- - rch analog negative input 1 pin (when die1 bit = ?l?, this pin must be open.) ( note 3 ) lin2+ i lch analog positive i nput 2 pin (die2 bit = ?h?) 69 lin2 i lch analog input 2 pin (die2 bit = ?l?) 70 lin2- - lch analog negative input 2 pin (when die2 bit = ?l?, this pin must be open.) ( note 3 ) rin2+ i rch analog positive i nput 2 pin (die2 bit = ?h?) 71 rin2 i rch analog input 2 pin (die2 bit = ?l?) 72 rin2- - rch analog negative input 2 pin (when die2 bit = ?l?, this pin must be open.) ( note 3 ) 73 tst17 i test pin this pin must be open. 74 tst18 i test pin this pin must be open. 75 vss1 - ground pin, 0v 76 avdd1 - analog power supply pin, 3.0v 3.6v 77 vrefh1 i positive voltage reference input pin, avdd1 78 vcom o common voltage output pin, avdd1x1/2 large external capacitor around 2.2f is used to reduce power-supply noise. 79 tst19 i test pin this pin must be open. 80 tst20 i test pin this pin must be open. note 1. this pin becomes ovf pin when ovfe bit is set to ?1?. note 2. this pin becomes dzf pin when ovfe bit is set to ?0?. note 3. this pin becomes analog negative input pin in differential input mode, and becomes output pin invert the positive input pin in single-end input mode. this pin must be open in single-end input mode. note 4. all digital input pins except for pull-down must not be left floating.
[ak4611] ms1050-e-02 2010/06 - 9 - absolute maximum ratings (vss1=vss2=vss3=vss4=0v; note 5 ) parameter symbol min max units power supplies analog digital output buffer avdd1,2 dvdd tvdd1,2 -0.3 -0.3 -0.3 4.2 2.2 4.2 v v v input current (any pins except for supplies) iin - 10 ma analog input voltage vina -0.3 avdd1,2+0.3 v digital input voltage (tst2,m/s,pdn,xti/mcki,lrck,bick, sdti1,sdti2,sdti3,sd ti4,tst7,tst8, dvmpd pins) (tst1,tst3,tst4,tst5,cad0,cad1,i2c, cclk/scl,csn,cdti/sda pins) vind1 vind2 -0.3 -0.3 tvdd1+0.3 tvdd2+0.3 v v ak4611eq ta -20 85 c ambient temperature (power applied) AK4611VQ ta -40 105 c storage temperature tstg -65 150 c note 5. all voltages with respect to ground. vss1, vss2, vss3 and vss4 must be connected to the same analog ground plane. avdd1 and avdd2 must be the same voltage. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=vss3=vss4=0v; note 5 ) parameter symbol min typ max units power supplies ( note 6 ) analog digital i/o buffer 1 (stereo mode & normal speed mode) i/o buffer 1 (except stereo mode & normal speed mode) i/o buffer 2 avdd1,2 dvdd tvdd1 tvdd1 tvdd2 3.0 1.6 dvdd 3.0 dvdd 3.3 1.8 3.3 3.3 3.3 3.6 2.0 3.6 3.6 3.6 v v v v v note 6. the power up sequence between avdd1, avdd2, dvdd, tvdd1 and tvdd2 is not critical. each power supplies should be powered up during the pdn pin = ?l?. the pdn pin should be ?h? after all power supplies are powered up. all power supplies should be powered on, only a part of these power supplies cannot be powered off. (power off means power supplies equal to ground or power supplies are floating.) do not turn off only the ak4611 under the condition that a surrounding device is powered on and the i2c bus is in use. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4611] ms1050-e-02 2010/06 - 10 - analog characteristics (ta=25 c; avdd1=avdd2=tvdd1=tvdd2=3.3v, dvdd =1.8v; vss1=vss2=0v; vrefh1=avdd1, vrefh2=avdd2; fs=48khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at 48khz, 20hz~40khz at fs=96khz, 20hz~4 0khz at fs=192khz; unless otherwise specified) parameter min typ max units adc analog input characteristics (single inputs) resolution 24 bits -1dbfs 84 92 db fs=48khz bw=20khz -60dbfs 40 -1dbfs 83 91 db fs=96khz bw=40khz -60dbfs 37 -1dbfs 91 s/(n+d) fs=192khz bw=40khz -60dbfs 37 dr (-60dbfs with a-weighted) 95 103 db s/n (a-weighted) 95 103 db interchannel isolation 90 110 db interchannel gain mismatch 0.1 0.5 db gain drift 40 - ppm/ c input voltage ain=0.65xvrefh1 1.94 2.15 2.37 vpp input resistance 7 9 k power supply rejection ( note 7 ) 50 db adc analog input characteristics (differential inputs) -1dbfs 88 97 db fs=48khz bw=20khz -60dbfs 40 db -1dbfs 86 94 fs=96khz bw=40khz -60dbfs 37 -1dbfs 94 s/(n+d) fs=192khz bw=40khz -60dbfs 37 dr (-60dbfs with a-weighted) 96 104 db s/n (a-weighted) 96 104 db interchannel isolation 90 110 db interchannel gain mismatch 0.1 0.5 db gain drift 40 - ppm/ c input voltage ain=0.65xvrefh1 ( note 8 ) 1.94 2.15 2.37 vpp input resistance 11 13 k power supply rejection ( note 7 ) 50 db common mode rejection ratio (cmrr) ( note 9 ) 74 db dac analog output characteristics (single outputs) resolution 24 bits 0dbfs 84 94 db fs=48khz bw=20khz -60dbfs 44 0dbfs 86 92 fs=96khz bw=40khz -60dbfs 41 0dbfs 92 s/(n+d) fs=192khz bw=40khz -60dbfs 41 dr (-60dbfs with a-weighted) 97 105 db s/n (a-weighted) 97 105 db interchannel isolation 90 110 db interchannel gain mismatch 0.1 0.5 db gain drift 20 - ppm/ c output voltage aout=0.63xvrefh2 1.87 2.08 2.29 vpp load resistance (ac load) 5 k load capacitance 30 pf power supply rejection ( note 7 ) 50 db
[ak4611] ms1050-e-02 2010/06 - 11 - dac analog output characteri stics (differential outputs) 0dbfs 90 100 db fs=48khz bw=20khz -60dbfs 45 0dbfs 88 98 fs=96khz bw=40khz -60dbfs 42 0dbfs 98 s/(n+d) fs=192khz bw=40khz -60dbfs 42 dr (-60dbfs with a-weighted) 100 108 db s/n (a-weighted) 100 108 db interchannel isolation 90 110 db interchannel gain mismatch 0 0.5 db gain drift 20 - ppm/ c output voltage aout=0.63xvrefh2 ( note 8 ) 1.87 2.08 2.29 vpp load resistance ( note 10 ) 2 k load capacitance 30 pf power supply rejection ( note 7 ) 50 db note 7. psr is applied to avdd1, avdd2, dvdd, tvdd1 and tvdd2 with 1khz, 50mvpp. vrefh1 and vrefh2 pins are held a constant voltage +3.3v. note 8. this value is (lin+) ? (lin-) and (rin+) ? (rin -). the voltage is proportional to vrefh1, vrefh2 voltage. note 9. vrefh1 and vrefh2 are held +3.3v, the input bias voltage is set to avdd1, 2 x 0.5. the 1khz, 0.96vpp signal is applied to lin- and lin+ with same phase (e.g. shorted) or rin- and rin+. the cmrr is measured as the attenuation level from 0db = -7dbfs (since the normal 0.96vpp = -7dbfs). this value is guaranteed but not tested. note 10. for ac-load. in the case of dc-load is 5k ? . note 11. this value is load capacitance for output pin to gnd. in differential mode, this value should be estimated to be twice, because load capacitance exists to gnd and between the differential pin. parameter min typ max units power supplies power supply current normal operation (pdn pin = ?h?) avdd1+avdd2 fs=48khz, 96khz, 192khz dvdd fs=48khz fs=96khz fs=192khz tvdd1+tvdd2 fs=48khz fs=96khz fs=192khz power-down mode (pdn pin = ?l?, dvmpd = ?l?) ( note 12 ) avdd1+avdd2+dvdd+tvdd1+tvdd2 (pdn pin = ?l?, dvmpd = ?h?) ( note 12 ) avdd1+avdd2+dvdd+tvdd1+tvdd2 63.0 12.0 17.0 28.0 6.0 7.0 7.0 200 10 125.0 24.0 35.0 55.0 8.0 9.5 9.5 550 200 ma ma ma ma ma ma ma a a note 12. in the power-down mode, all digital input pins including clock pins are held vss3 (tst1, tst3, tst4, tst5, cad0, cad1, i2c, csn, cclk, cdti pins), vss4 (tst 2, m/s, mcki, lrck, bick, sdti1, sdti2, sdti3, sdti4,tst7, tst8).
[ak4611] ms1050-e-02 2010/06 - 12 - filter characteristics (fs=48khz) ( ta= tmin tmax ; avdd1=avdd2=3.0 3.6v, dvdd=1.6 2.0v, tvdd1=tvdd2=1.6 3.6v; dem=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 13 ) 0.1db ? 0.2db ? 3.0db pb 0 - - - 20.0 23.0 18.9 - - khz khz khz stopband ( note 13 ) sb 28 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay distortion gd - 0 - s group delay ( note 14 ) gd - 16 - 1/fs adc digital filter (hpf): frequency response ( note 13 ) ? 3db ? 0.1db fr - - 1.0 6.5 - - hz hz dac digital filter (lpf): passband ( note 13 ) 0.06db ? 6.0db pb 0 - - 24.0 21.8 - khz khz stopband ( note 13 ) sb 26.2 - - khz passband ripple pr - - 0.06 db stopband attenuation sa 54 - - db group delay distortion gd - 0 - s group delay ( note 14 ) gd - 22 - 1/fs dac digital filter + analog filter: frequency response ( note 15 ) 20khz fr - -0.1 - db filter characteristics (fs=96khz) ( ta= tmin tmax ; avdd1=avdd2=3.0 3.6v, dvdd=1.6 2.0v, tvdd1=tvdd2=1.6 3.6v; dem=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 13 ) 0.1db ? 0.2db ? 3.0db pb 0 - - - 40.0 46.0 37.8 - - khz khz khz stopband ( note 13 ) sb 56 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay distortion gd - 0 - s group delay ( note 14 ) gd - 16 - 1/fs adc digital filter (hpf): frequency response ( note 13 ) ? 3db ? 0.1db fr - - 2.0 13.0 - - hz hz dac digital filter (lpf): passband ( note 13 ) 0.06db ? 6.0db pb 0 - - 48.0 43.6 - khz khz stopband ( note 13 ) sb 52.4 - - khz passband ripple pr - - 0.06 db stopband attenuation sa 54 - - db group delay distortion gd - 0 - s group delay ( note 14 ) gd - 22 - 1/fs dac digital filter + analog filter: frequency response ( note 15 ) 40khz fr - -0.3 - db
[ak4611] ms1050-e-02 2010/06 - 13 - filter characteristics (fs=192khz) ( ta= tmin tmax ; avdd1=avdd2=3.0 3.6v, dvdd=1.6 2.0v, tvdd1=tvdd2=1.6 3.6v; dem=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 13 ) 0.1db ? 0.2db ? 3.0db pb 0 - - - 57.0 90.3 56.6 - - khz khz khz stopband ( note 13 ) sb 112 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 70 - - db group delay distortion gd - 0 - s group delay ( note 14 ) gd - 16 - 1/fs adc digital filter (hpf): frequency response ( note 13 ) ? 3db ? 0.1db fr - - 4.0 26.0 - - hz hz dac digital filter (lpf): passband ( note 13 ) 0.06db ? 6.0db pb 0 - - 96.0 87.0 - khz khz stopband ( note 13 ) sb 104.9 - - khz passband ripple pr - - 0.06 db stopband attenuation sa 54 - - db group delay distortion gd - 0 - s group delay ( note 14 ) gd - 22 - 1/fs dac digital filter + analog filter: frequency response ( note 15 ) 80khz fr - -1 - db note 13. the passband and stopband frequencies scale with fs (sampling frequency). for example, adc: passband ( 0.1db) = 0.39375 x fs (@ fs=48khz), dac: passband ( 0.06db) = 0.45412 x fs. note 14. the calculated delay time is resulting from digital filte ring. for the adc, this time is from the input of an analog signal to the setting of 24bit data for both channels to the adc output register. for the dac, this time is from setting the 24 bit data both channels at the input register to the output of an analog signal. note 15. the reference frequency is 1khz.
[ak4611] ms1050-e-02 2010/06 - 14 - dc characteristics (ta= tmin tmax ; avdd1=avdd2=3.0 3.6; dvdd=1.6 2.0v; tvdd1=tvdd2=1.6 3.6v) parameter symbol min typ max units tvdd1,tvdd2 2.2v high-level input voltage (tst2, m/s, pdn, mcki, lrck, bick, sdti1, sdti2, sdti3, sdti4,tst7, tst8, dvmpd pins) (tst1,tst3,tst4,tst5,cad0,cad1,i2c, csn,cclk, cdti pins) low-level input voltage (tst2, m/s, pdn, mcki, lrck, bick, sdti1, sdti2, sdti3, sdti4,tst7, tst8, dvmpd pins) (tst1,tst3,tst4,tst5,cad0,cad1,i2c, csn,cclk, cdti pins) vih vih vil vil 80%tvdd1 80%tvdd2 - - - - - - - - 20%tvdd1 20%tvdd2 v v v v tvdd1,tvdd2 > 2.2v high-level input voltage (tst2, m/s, pdn, mcki, lrck, bick, sdti1, sdti2, sdti3, sdti4,tst7, tst8, dvmpd pins) (tst1,tst3,tst4,tst5,cad0,cad1,i2c, csn,cclk, cdti pins) low-level input voltage (tst2, m/s, pdn, mcki, lrck, bick, sdti1, sdti2, sdti3, sdti4,tst7, tst8, dvmpd pins) (tst1,tst3,tst4,tst5,cad0,cad1,i2c, csn,cclk, cdti pins) vih vih vil vil 70%tvdd1 70%tvdd2 - - - - - - - - 30%tvdd1 30%tvdd2 v v v v high-level output voltage (sdto1,sdto2,tst6, lrck, bick, mcko pins: iout=-100a) (cdto pin: iout=-100a) (dzf1/ovf1, dzf2/ovf2 pins: iout=-100a) low-level output voltage (sdto1,sdto2,tst6, lrck, bick, mcko, cdto, dzf1, dzf2/ovf pins: iout= 100a) (sda pin, 2.0v tvdd2 3.6v iout= 3ma) (sda pin, 1.6v tvdd2<2.0v iout= 3ma) voh voh vol vol vol tvdd1-0.5 tvdd2-0.5 avdd2-0.5 - - - - - - - - 0.5 0.4 20%tvdd2 v v v v v v input leakage current iin - - 10 a
[ak4611] ms1050-e-02 2010/06 - 15 - switching characteristics (ta= tmin tmax ; avdd1=avdd2=3.0 3.6; dvdd=1.6 2.0v; tvdd1=1.6 3.6v, tvdd2=1.6 3.6v; c l =20pf; unless otherwise specified) parameter symbol min typ max units master clock timing crystal resonator frequency fxtal 11.2896 24.576 mhz mcko output frequency (tvdd1 3.0v) duty fmck dmck 5.6448 40 50 24.576 60 mhz % external clock 256fsn: pulse width low pulse width high 384fsn: pulse width low pulse width high 512fsn, 256fsd, 128fsq: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8.192 32 32 12.288 22 22 16.384 16 16 12.288 18.432 24.576 mhz ns ns mhz ns ns mhz ns ns mcko output frequency (tvdd1 3.0v) duty ( note 16 ) fmck fmck dmck 4.096 12.288 40 50 12.288 24.576 60 mhz mhz % lrck timing (slave mode) stereo mode (tdm0 bit = ?0?, tdm1 bit = ?0?) normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 64 128 45 48 96 192 55 khz khz khz % tdm512 mode ( note 17 ) (tdm0 bit = ?0?, tdm1 bit = ?1?) lrck frequency ?h? time ?l? time fsn tlrh tlrl 32 1/512fs 1/512fs 48 khz ns ns tdm256 mode ( note 18 ) (tdm0 bit = ?1?, tdm1 bit = ?0?) lrck frequency ?h? time ?l? time fsd tlrh tlrl 64 1/256fs 1/256fs 96 khz ns ns tdm128 mode ( note 19 ) (tdm0 bit = ?1?, tdm1 bit = ?1?) lrck frequency ?h? time ?l? time fsq tlrh tlrl 128 1/128fs 1/128fs 192 khz ns ns
[ak4611] ms1050-e-02 2010/06 - 16 - parameter symbol min typ max units lrck timing (master mode) stereo mode (tdm0 bit = ?0?, tdm1 bit = ?0?) normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 64 128 - 50 48 96 192 - khz khz khz % tdm512 mode ( note 17 ) (tdm0 bit = ?0?, tdm1 bit = ?1?) lrck frequency ?h? time ( note 20 ) fsn tlrh 32 1/16fs 48 khz ns tdm256 mode ( note 18 ) (tdm0 bit = ?1?, tdm1 bit = ?0?) lrck frequency ?h? time ( note 20 ) fsd tlrh 64 1/8fs 96 khz ns tdm128 mode ( note 19 ) (tdm0 bit = ?1?, tdm1 bit = ?1?) lrck frequency ?h? time ( note 20 ) fsq tlrh 128 1/4fs 192 khz ns note 16. except the case of div bit = ?0?. note 17. please use for normal speed mode. master clock should be input the 512fs in master mode. note 18. please use for double speed mode. note 19. please use for quad speed mode. note 20. if the format is i 2 s, it is ?l? time.
[ak4611] ms1050-e-02 2010/06 - 17 - parameter symbol min typ max units audio interface timing (slave mode) stereo mode (tdm0 bit = ?0?, tdm1 bit = ?0?) (tvdd1= 1.6v 3.6v) bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 21 ) bick ? ? to lrck edge ( note 21 ) lrck to sdto(msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 324 130 130 20 20 50 50 80 80 ns ns ns ns ns ns ns ns ns (tvdd1= 3.0v 3.6v) bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 21 ) bick ? ? to lrck edge ( note 21 ) lrck to sdto(msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 81 33 33 23 23 10 10 23 23 ns ns ns ns ns ns ns ns ns tdm512 mode (tdm0 bit = ?0?, tdm1 bit = ?1?) (tvdd1= 3.0v 3.6v) ( note 17 ) bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 21 ) bick ? ? to lrck edge ( note 21 ) sdto setup time bick ? ? sdto hold time bick ? ? sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tbss tbsh tsdh tsds 40 16 16 10 10 6 5 10 10 ns ns ns ns ns ns ns ns ns ns tdm256 mode (tdm0 bit = ?1?, tdm1 bit = ?0?) (tvdd1= 3.0v 3.6v) ( note 18 ) bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 21 ) bick ? ? to lrck edge ( note 21 ) sdto setup time bick ? ? sdto hold time bick ? ? sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tbss tbsh tsdh tsds 40 16 16 10 10 6 5 10 10 ns ns ns ns ns ns ns ns ns tdm128 mode (tdm0 bit = ?1?, tdm1 bit = ?1?) (tvdd1= 3.0v 3.6v) ( note 19 ) bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 21 ) bick ? ? to lrck edge ( note 21 ) sdto setup time bick ? ? sdto hold time bick ? ? sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tbss tbsh tsdh tsds 40 16 16 10 10 6 5 10 10 ns ns ns ns ns ns ns ns ns
[ak4611] ms1050-e-02 2010/06 - 18 - parameter symbol min typ max units audio interface timing (master mode) stereo mode (tdm0 bit = ?0?, tdm1 bit = ?0?) (tvdd1= 1.6v 3.6v) bick frequency bick duty bick ? ? to lrck bick ? ? to sdto sdti hold time sdti setup time fbck dbck tmblr tbsd tsdh tsds - - ? 40 ? 70 50 50 64fs 50 - - - - - - 40 70 - - hz % ns ns ns ns (tvdd1= 3.0v 3.6v) bick frequency bick duty bick ? ? to lrck bick ? ? to sdto sdti hold time sdti setup time fbck dbck tmblr tbsd tsdh tsds - - ? 23 ? 23 10 10 64fs 50 - - - - - - 23 23 - - hz % ns ns ns ns tdm512 mode (tdm0 bit = ?0?, tdm1 bit = ?1?) (tvdd1= 3.0v 3.6v) ( note 17 ) bick frequency bick duty bick ? ? to lrck sdto setup time bick ? ? sdto hold time bick ? ? sdti hold time sdti setup time fbck dbck tmblr tbss tbsh tsdh tsds - - -10 6 5 10 10 512fs 50 - - - - - - 10 - - - - hz % ns ns ns ns ns tdm256 mode (tdm0 bit = ?1?, tdm1 bit = ?0?) (tvdd1= 3.0v 3.6v) ( note 18 ) bick frequency bick duty bick ? ? to lrck sdto setup time bick ? ? sdto hold time bick ? ? sdti hold time sdti setup time fbck dbck tmblr tbss tbsh tsdh tsds - - ? 10 6 5 10 10 256fs 50 - - - - - - - 10 - - - - hz % ns ns ns ns ns tdm128 mode (tdm0 bit = ?1?, tdm1 bit = ?1?) (tvdd1= 3.0v 3.6v) ( note 19 ) bick frequency bick duty bick ? ? to lrck sdto setup time bick ? ? sdto hold time bick ? ? sdti hold time sdti setup time fbck dbck tmblr tbss tbsh tsdh tsds - - ? 10 6 5 10 10 128fs 50 - - - - - - - 10 - - - - hz % ns ns ns ns ns note 21. bick rising edge must not occur at the same time as lrck edge.
[ak4611] ms1050-e-02 2010/06 - 19 - parameter symbol min typ max units control interface timing (4-wire serial mode): cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? cdto delay csn ? ? to cdto hi-z tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 40 40 150 50 50 50 70 ns ns ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 22 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - 400 - - - - - - - 1.0 0.3 - 50 400 khz s s s s s s s s s s ns pf power-down & reset timing pdn pulse width ( note 23 ) pdn ? ? to sdto valid ( note 24 ) tpd tpdv 150 518 ns 1/fs note 22. data must be held for sufficient time to bridge the 300 ns transition time of scl. note 23. the ak4611 can be reset by setting the pdn pin to ?l? upon power-up. note 24. these cycles are the numbers of lrck rising from the pdn pin rising. note 25. i 2 c-bus is a trademark of nxp b.v.
[ak4611] ms1050-e-02 2010/06 - 20 - timing diagram 1/fclk tclkl vih tclkh mcki vil 1/fsn, 1/fsd, 1/fsq lrck vih vil tbck tbckl vih tbckh bick vil tdlrkl tdlrkh duty = tdlrkh (or tdlrkl) x fs x 100 figure 3. clock timing (tdm1/0 bit = ?00? & slave mode) 1/fclk tclkl vih tclkh mcki vil 1/fs lrck vih vil tlrl tlrh tbck tbckl vih tbckh bick vil figure 4. clock timing (except tdm1/0 bit = ?00? & slave mode)
[ak4611] ms1050-e-02 2010/06 - 21 - 1/fclk tclkl vih tclkh mcki vil 1/fmck 50%tvdd1 mcko tdmckl tdmckh dmck = tdmckh (or tdmckl) x fmck x 100 1/fbck tdbckl tdbckh bick 50%tvdd1 1/fs lrck 50%tvdd1 tdlrkl tdlrkh dlrk = tdlrkh (or tdlrkl) x fs x 100 dbck = tdbckh (or tdbckl) x fs x 100 figure 5. clock timing (tdm1/0 bit = ?00? & master mode) 1/fclk tclkl vih tclkh mcki vil 1/fmck 50%tvdd1 mcko tdmckl tdmckh dmck = tdmckh (or tdmckl) x fmck x 100 1/fs lrck 50%tvdd1 tlrh 1/fbck tdbckl tdbckh bick 50%tvdd1 dbck = tdbckh (or tdbckl) x fs x 100 figure 6. clock timing (except tdm1/0 bit = ?00? & master mode)
[ak4611] ms1050-e-02 2010/06 - 22 - tlrb lrck vih bick vil tlrs sdto 50%tvdd1 tbsd vih vil tblr tsds sdti vih vil tsdh figure 7. audio interface timing (t dm1/0 bit = ?00? & slave mode) tlrb lrck vih bick vil sdto 50%tvdd1 tbss vih vil tblr tsds sdti vih vil tsdh tbsh figure 8. audio interface timing (excep t tdm1/0 bit = ?00? & slave mode)
[ak4611] ms1050-e-02 2010/06 - 23 - lrck bick sdto tbsd tmblr 50%tvdd1 50%tvdd1 50%tvdd1 sdti tsdh tsds vih vil figure 9. audio interface timing (t dm1/0 bit = ?00? & master mode) lrck bick sdto tbsh tmblr 50%tvdd1 50%tvdd1 50%tvdd1 sdti tsdh tsds vih vil tbss figure 10. audio interface timing (except tdm1/0 bit = ?00? & master mode)
[ak4611] ms1050-e-02 2010/06 - 24 - csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w cdto hi-z tcsh figure 11. write command input timing (4-wire serial mode) csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 cdto hi-z d2 tcss figure 12. write data input timing (4-wire serial mode)
[ak4611] ms1050-e-02 2010/06 - 25 - csn vih vil cclk vih vil cdti vih vil a0 cdto a1 50%tvdd2 tdcd d7 d6 hi-z figure 13. read data output timing1(4-wire serial mode) csn vih vil tcsh cclk vih vil cdti vih tcsw vil cdto 50%tvdd2 d2 d1 d0 tccz hi-z tcss figure 14. read data output timing2(4-wire serial mode)
[ak4611] ms1050-e-02 2010/06 - 26 - thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 15. i 2 c bus mode timing tpd vil pdn tpdv sdto 50%tvdd1 vih figure 16. power-down & reset timing
[ak4611] ms1050-e-02 2010/06 - 27 - operation overview system clock it is possible to select the clock source either extra clock input or x?tal input for the ak4611. ( figure 17 , figure 18 ) the external clocks which are required to operate the ak4611 in slave mode are mclk, lrck and bick. mclk should be synchronized with lrck but the phase is not critical. there are two methods to set mclk frequency. in manual setting mode (acks bit= ?0?: default), the sampling speed is set by dfs0, dfs1 ( table 1 ). the frequency of mclk at each sampling speed is set automatically. ( table 3 , table 4 , table 5 ). in auto setting mode (acks bit= ?1?), as mclk frequency is detected automatically ( table 6 ) and the internal master clock attains the appropriate frequency ( table 7 ), so it is not necessary to set dfs. in master mode, only mclk is required. master clock inpu t frequency should be set with the cks1-0 bits, and the sampling speed should be set by the dfs1-0 bits. the frequencies and the duties of the clocks (lrck, bick) are not stabile immediately after setting ck s1-0 bits and dfs1-0 bits up. after exiting reset at power-up in slave mode, the ak461 1 is in power-down mode un til mclk and lrck are input. if the clock is stopped, click noise occurs when restarting the clock. mute the digital output externally if the click noise influences system applications. dfs1 dfs0 sampling speed mode (fs) 0 0 normal speed mode 32khz~48khz 0 1 double speed mode 64khz~96khz (default) 1 0 quad speed mode 128khz~192khz 1 1 n/a - (n/a: not available) table 1. sampling speed (manual setting mode) cks1 cks0 normal speed mode double speed mode quad speed mode 0 0 256fs 256fs 128fs 0 1 384fs 256fs 128fs 1 0 512fs 256fs 128fs (default) 1 1 512fs 256fs 128fs table 2. master clock input frequency select (master mode) lrck mclk (mhz) bick (mhz) fs 256fs 384fs 512fs 64fs 32.0khz 8.1920 12.2880 16.3840 2.0480 44.1khz 11.2896 16.9344 22.5792 2.8224 48.0khz 12.2880 18.4320 24.5760 3.0720 table 3. system clock example (normal speed mode @manual setting mode)
[ak4611] ms1050-e-02 2010/06 - 28 - lrck mclk (mhz) bick (mhz) fs 256fs 64fs 88.2khz 22.5792 5.6448 96.0khz 24.5760 6.1440 table 4. system clock example (double speed mode @manual setting mode) lrck mclk (mhz) bick (mhz) fs 128fs 64fs 176.4khz 22.5792 11.2896 192.0khz 24.5760 12.2880 table 5. system clock example (quad speed mode @manual setting mode) mclk sampling speed mode 512fs normal speed mode 256fs double speed mode 128fs quad speed mode table 6. sampling speed (auto setting mode) lrck mclk (mhz) fs 128fs 256fs 512fs sampling speed mode 32.0khz - - 16.3840 44.1khz - - 22.5792 48.0khz - - 24.5760 normal speed mode 88.2khz - 22.5792 - 96.0khz - 24.5760 - double speed mode 176.4khz 22.5792 - - 192.0khz 24.5760 - - quad speed mode table 7. system clock example (auto setting mode)
[ak4611] ms1050-e-02 2010/06 - 29 - clock source the clock for the xti pin can be generated by the two methods. 1) external clock xti xto ak4611 external clock figure 17. external clock mode note: input clock must not exceed tvdd1. 2) x?tal xti xto ak4611 figure 18. x?tal mode note: external capacitance depends on the crystal oscillator (typ. 10pf) tvdd1 should be used in the range of 3.0 ~ 3.6v in x?tal mode.
[ak4611] ms1050-e-02 2010/06 - 30 - differential / single-end input selection the ak4611 supports the differential input ( figure 19 ) by setting die1-2 bits = ?1?, supports the single-end input ( figure 20 ) by setting die1-2 bits = ?0?. in differential input mode, two input pins must not be connected to a signal input in combination with a vcom voltage. when single-end input mode , l/rin1-2 pins should be open, because l/rin1-2 pins output an invert signal of the input signal. the ak4611 includes an anti-aliasing filter (rc filter) for both differential input and the single-end input. scf l/rin+ l/rin- lpf lpf ak4611 figure 19. differential input (die1-2 bit = ?1?) scf l/rin l/rin- lpf ak4611 (open) figure 20. single-end input (die1-2 bit = ?0?) differential / single-end output selection the ak4611 supports the differential output ( figure 21 ) by setting doe1-4 bits = ?1?, and the single-end output ( figure 22 ) by setting doe1-4 bits = ?0?. when single-end output mode, l/rout1-4 pins should be open, because of l/rout1-4 pins outputs vcom voltage. the internal analog filters remove most of the noise beyond the audio passband generated by the delta-sigma modulator of a dac in single-end input mode. ther e is no internal analog filter for differential output. use external analog filters if needed to remove this noise. scf l/rout+ l/rout- ak4611 figure 21. differential output (doe1-4 bit = ?1?) scf l/rout l/rout- lpf diff to single ak4611 (open) figure 22. single-end output (doe1-4 bit = ?0?)
[ak4611] ms1050-e-02 2010/06 - 31 - de-emphasis filter the ak4611 has a digital de-emphasis filter (tc=50/15s) by an iir filter. the de-emphasis filter supports only normal speed mode. this filter corres ponds to three sampling frequ encies (32khz, 44.1khz, 48kh z). de-emphasi s of each dac can be set individually by registers, dac1(sdti1), dac2(sdti2), dac3(sdti3), dac4(sdti4). mode sampling speed mode dem11 (dem61-21) dem10 (dem60-20) dem 0 normal speed mode 0 0 44.1khz 1 normal speed mode 0 1 off (default) 2 normal speed mode 1 0 48khz 3 normal speed mode 1 1 32khz table 8. de-emphasis control digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 1.0hz at fs=48khz and scales with the sampling rate (fs). master clock output the ak4611 has a master clock output pin. if div bit = ?1?, the mcko pin output the frequency divided in half. div mcko 0 xti x1 1 xti x1/2 (default) table 9. the select of master clock output frequency master mode and slave mode master mode and slave mode are selected by setting the m/s pin. (master mode= ?h?, slave mode= ?l?) lrck and bick pins are outputs in master mode (m/s pin= ?h?) lrck and bick pins are inputs in slave mode (m/s pin= ?l?) pdn m/s pin lrck pin bick pin l input input l h ?l? output ?l? output l input input h h output output table 10. lrck and bick pins
[ak4611] ms1050-e-02 2010/06 - 32 - audio serial interface format (1) stereo mode when tdm1-0 bits = ?00?, ten modes can be selected by the dif2-0 bits as shown in table 11 . in all modes the serial data is msb-first, 2?s compliment format. the data sdto1-2 is clocked out on the falling edge of bick and the sdti1-4 is latched on the rising edge of bick. mode3/4/8/9/13/14/18/19/23/24/28/29/33/34/38/39 in sdti input formats can be used for 16-20bit data by zeroing the unused lsbs. lrck bick mode m/s tdm1 tdm0 dif2 dif1 dif0 sdto1-2 sdti1-4 i/o i/o 0 0 0 0 0 0 0 24bit, left justified 16bit, right justified h/l i 32fs i 1 0 0 0 0 0 1 24bit, left justified 20bit, right justified h/l i 48fs i 2 0 0 0 0 1 0 24bit, left justified 24bit, right justified h/l i 48fs i 3 0 0 0 0 1 1 24bit, left justified 24bit, left justified h/l i 48fs i 4 0 0 0 1 0 0 24bit, i 2 s 24bit, i 2 s l/h i 48fs i (default) 5 1 0 0 0 0 0 24bit, left justified 16bit, right justified h/l o 64fs o 6 1 0 0 0 0 1 24bit, left justified 20bit, right justified h/l o 64fs o 7 1 0 0 0 1 0 24bit, left justified 24bit, right justified h/l o 64fs o 8 1 0 0 0 1 1 24bit, left justified 24bit, left justified h/l o 64fs o 9 1 0 0 1 0 0 24bit, i 2 s 24bit, i 2 s l/h o 64fs o table 11. audio data formats (stereo mode) note. tvdd1 which is the power of i/o buffer should be kept in the range of 1.6v~3.6v at normal speed mode in stereo mode. tvdd1 should be kept in the range of 3.0v~3.6v at double speed mode and quad speed mode.
[ak4611] ms1050-e-02 2010/06 - 33 - (2) tdm mode the audio serial interface format is set in tdm mode by th e tdm1-0 bits = ?01?. five m odes can be selected by the dif2-0 bits as shown in table 12 . in all modes the serial data is msb-first, 2?s compliment format. the sdto1 is clocked out on the rising edge of bick and the sdti1/2/3 are latched on the rising edge of bick. in the tdm512 mode (fs = 48khz), the serial data of all adc (four channels) is output to the sdto1 pin. sdto2 pin = ?l?. and the serial data of all dac (eight channels) is input to the sdti1 pin. the input data to sdti2-4 pins are ignored. bick should be fixed to 512fs. ?h? time and ?l? time of lrck should be 1/512fs at least. tdm256 mode can be set by tdm1-0 bits as show in table 13 . in the tdm256 mode (fs = 48khz), the serial data of all adc (four channels) is output to the sdto1 pin. sdto2 pin = ?l?. and the serial data of dac (eight channels; l1, r1, l2, r2, l3, r3, l4, r4) is input to the sdti1 pin. the input data to sdti2-4 pins are ignored. bick should be fixed to 256fs. ?h? time and ?l? time of lrck should be 1/256fs at least. tdm128 mode can be set by tdm1-0 bits as show in table 14 . in tdm128 mode (fs=192khz), the serial data of four adc (four channels; l1, r1, l2, r2) is output to the sdto1 pin. the sdto2 pin = ?l?. and the serial data of dac (four channels; l1, r1, l2, r2) is input to the sdti1 pin and the serial data of dac (four channels; l3, r3, l4, r4) is input to the sdti2 pin. the input data to sdti3-4 pins are ignored. bick should be fixed to 128fs. ?h? time and ?l? time of lrck should be 1/128fs at least. lrck bick mode m/s tdm1 tdm0 dif2 dif1 dif0 sdto1-2 sdti1-4 i/o i/o 10 0 0 1 0 0 0 24bit, left justified 16bit, right justified i 512fs i 11 0 0 1 0 0 1 24bit, left justified 20bit, right justified i 512fs i 12 0 0 1 0 1 0 24bit, left justified 24bit, right justified i 512fs i 13 0 0 1 0 1 1 24bit, left justified 24bit, left justified i 512fs i 14 0 0 1 1 0 0 24bit, i 2 s 24bit, i 2 s i 512fs i 15 1 0 1 0 0 0 24bit, left justified 16bit, right justified o 512fs o 16 1 0 1 0 0 1 24bit, left justified 20bit, right justified o 512fs o 17 1 0 1 0 1 0 24bit, left justified 24bit, right justified o 512fs o 18 1 0 1 0 1 1 24bit, left justified 24bit, left justified o 512fs o 19 1 0 1 1 0 0 24bit, i 2 s 24bit, i 2 s o 512fs o table 12. audio data formats (tdm512 mode)
[ak4611] ms1050-e-02 2010/06 - 34 - lrck bick mode m/s tdm1 tdm0 dif2 dif1 dif0 sdto1-2 sdti1-4 i/o i/o 20 0 1 0 0 0 0 24bit, left justified 16bit, right justified i 256fs i 21 0 1 0 0 0 1 24bit, left justified 20bit, right justified i 256fs i 22 0 1 0 0 1 0 24bit, left justified 24bit, right justified i 256fs i 23 0 1 0 0 1 1 24bit, left justified 24bit, left justified i 256fs i 24 0 1 0 1 0 0 24bit, i 2 s 24bit, i 2 s i 256fs i 25 1 1 0 0 0 0 24bit, left justified 16bit, right justified o 256fs o 26 1 1 0 0 0 1 24bit, left justified 20bit, right justified o 256fs o 27 1 1 0 0 1 0 24bit, left justified 24bit, right justified o 256fs o 28 1 1 0 0 1 1 24bit, left justified 24bit, left justified o 256fs o 29 1 1 0 1 0 0 24bit, i 2 s 24bit, i 2 s o 256fs o table 13. audio data formats (tdm256 mode) lrck bick mode m/s tdm1 tdm0 dif2 dif1 dif0 sdto1-2 sdti1-4 i/o i/o 30 0 1 1 0 0 0 24bit, left justified 16bit, right justified i 128fs i 31 0 1 1 0 0 1 24bit, left justified 20bit, right justified i 128fs i 32 0 1 1 0 1 0 24bit, left justified 24bit, right justified i 128fs i 33 0 1 1 0 1 1 24bit, left justified 24bit, left justified i 128fs i 34 0 1 1 1 0 0 24bit, i 2 s 24bit, i 2 s i 128fs i 35 1 1 1 0 0 0 24bit, left justified 16bit, right justified o 128fs o 36 1 1 1 0 0 1 24bit, left justified 20bit, right justified o 128fs o 37 1 1 1 0 1 0 24bit, left justified 24bit, right justified o 128fs o 38 1 1 1 0 1 1 24bit, left justified 24bit, left justified o 128fs o 39 1 1 1 1 0 0 24bit, i 2 s 24bit, i 2 s o 128fs o table 14. audio data formats (tdm128 mode) note. tvdd1 should be used in the range of 3.0v~3.6v in tdm mode.
[ak4611] ms1050-e-02 2010/06 - 35 - lrck bick(64fs) sdto ( o ) 0 1 2 16 17 18 24 25 31 0 1 2 16 17 18 24 25 31 0 23 1 22 0 23 22 8 7 6 0 23 sdti(i) 1 14 0 15 8 7 1 14 0 15 8 7 lch data rch data don?t care don?t care 8 7 6 sdto-23:msb, 0:lsb; sdti-15:msb, 0:lsb figure 23. mode 0/5 timing (stereo mode) lrck bick ( 64fs ) sdto ( o ) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti ( i ) 1 18 0 19 8 7 1 18 0 19 8 7 lch data rch data don?t care don?t care 12 11 10 sdto-23:msb, 0:lsb; sdti-19:msb, 0:lsb figure 24. mode 1/6 timing (stereo mode) lrck bick ( 64fs ) sdto ( o ) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti ( i ) 1 22 0 23 8 7 1 22 0 23 8 7 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 25. mode 2/7 timing (stereo mode) lrck bick ( 64fs ) sdto ( o ) 0 1 2 21 22 23 24 31 0 1 2 0 23 1 22 1 23 22 23 sdti ( i ) 22 23 0 22 23 23:msb, 0:lsb lch data rch data don?t care 2 2 1 28 29 30 23 0 22 23 24 31 1 0 don?t care 2 21 28 29 30 0 figure 26. mode 3/8 timing (stereo mode)
[ak4611] ms1050-e-02 2010/06 - 36 - lrck bick ( 64fs ) sdto ( o ) 0 1 2 3 22 23 24 25 0 0 1 sdti ( i ) 31 29 30 23 22 1 22 23 0 23:msb, 0:lsb lch data rch data don?t care 2 2 1 0 2 3 22 23 24 25 0 31 29 30 23 22 1 22 23 0 don?t care 2 21 0 1 figure 27. mode 4/9 timing (stereo mode) bick ( 512fs ) sdto1 ( o ) sdti1 ( i ) 2 2 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 22 0 r1 32 bick 2 3 2 3 32 bick 32 bick 32 bick 32 bick 2 2 2 3 14 0 15 14 0 15 14 0 1 5 14 0 15 14 0 1 5 14 0 1 5 14 0 15 14 0 1 5 2 2 0 l2 32 bick 2 2 0 r2 32 bick 2 3 2 3 1 5 lrck ( mode10 ) 51 2bick lrck ( mode15 ) 32 bick 32 bick 32 bick 32 bick figure 28. mode 10/15 timing (tdm512 mode) bick ( 512fs ) sdto1 ( o ) sdti1 ( i ) 2 2 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 22 0 r1 32 bick 2 3 2 3 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 2 2 2 3 1 8 0 1 9 1 8 0 1 9 1 8 0 1 9 1 8 0 1 9 1 8 0 1 9 1 8 0 1 9 1 8 0 1 9 1 8 0 1 9 2 2 0 l2 32 bick 2 2 0 r2 32 bick 2 3 2 3 19 lrck ( mode11 ) 51 2bick lrck ( mode16 ) figure 29. mode 11/16 timing (tdm512 mode) bick ( 512fs ) sdto1 ( o ) sdti1 ( i ) 2 2 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 22 0 r1 32 bick 2 3 2 3 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 2 2 2 3 2 2 0 2 3 2 2 0 2 3 2 2 0 2 3 2 2 0 2 3 22 0 2 3 22 0 2 3 2 2 0 2 3 2 2 0 2 3 2 2 0 l2 32 bick 2 2 0 r2 32 bick 2 3 2 3 23 lrck ( mode12 ) 51 2bick lrck ( mode17 ) figure 30. mode 12/17 timing (tdm512 mode)
[ak4611] ms1050-e-02 2010/06 - 37 - bick ( 512fs ) sdto1 ( o ) sdti1 ( i ) 2 2 0 l1 32 bick l1 32 bick r1 32 bick l2 3 2 bi c k r2 32 bick l3 3 2 bi c k r3 32 bic k l4 3 2 bi c k r4 32 bick 22 0 r1 32 bick 2 3 2 3 3 2 bi c k 32 bick 3 2 bi c k 32 bick 3 2 bi c k 32 bick 3 2 bi c k 32 bick 2 2 2 3 2 2 0 2 3 22 0 2 3 2 2 0 2 3 2 2 0 2 3 2 2 0 2 3 22 0 23 2 2 0 2 3 22 0 23 2 2 0 l2 32 bick 2 2 0 r2 32 bick 2 3 2 3 2 2 2 3 lrck ( mode13 ) 51 2bic k lrck ( mode18 ) figure 31. mode 13/18 timing (tdm512 mode) bick ( 512fs ) sdto1 ( o ) sdti1 ( i ) 2 3 0 l1 32 bick l1 32 bick r1 32 bick l2 3 2 bi c k r2 32 bick l3 3 2 bi c k r3 32 bic k l4 3 2 bi c k r4 32 bick 2 3 0 r1 32 bick 3 2 bi c k 32 bick 3 2 bi c k 32 bick 3 2 bi c k 32 bick 3 2 bi c k 32 bick 2 3 2 3 0 2 3 0 2 3 0 2 3 0 2 3 0 2 3 0 2 3 0 2 3 0 2 3 0 l2 32 bic k 2 3 0 r2 32 bick 2 3 lrck ( mode14 ) 51 2bic k lrck ( mode19 ) figure 32. mode 14/19 timing (tdm512 mode) bick(256fs) sdto1(o) sdti1(i) 22 0 l1 32 bick 14 0 l1 32 bick 14 0 r1 32 bick 14 0 l2 32 bick 14 0 r2 32 bick 14 0 l3 32 bick 14 0 r3 32 bick 14 0 l4 32 bick 14 0 r4 32 bick 22 0 r1 32 bick 22 23 15 15 15 15 15 23 15 15 15 23 15 lrck (mode20) 22 0 l2 32 bick 22 0 r2 32 bick 23 23 256 bick lrck (mode25) figure 33. mode 20/25 timing (tdm256 mode)
[ak4611] ms1050-e-02 2010/06 - 38 - bick(256fs) sdto1(o) sdti1(i) 22 0 l1 32 bick 18 0 l1 32 bick 18 0 r1 32 bick 18 0 l2 32 bick 18 0 r2 32 bick 18 0 l3 32 bick 18 0 r3 32 bick 18 0 l4 32 bick 18 0 r4 32 bick 22 0 r1 32 bick 22 23 19 19 19 19 19 23 19 19 19 23 19 lrck (mode21) 22 0 l2 32 bick 22 0 r2 32 bick 23 23 256 bick lrck (mode26) figure 34. mode 21/26 timing (tdm256 mode) bick(256fs) sdto1(o) sdti1(i) 22 0 l1 32 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 l4 32 bick 22 0 r4 32 bick 22 0 r1 32 bick 22 23 23 23 23 23 23 23 23 23 23 23 23 lrck (mode22) 22 0 l2 32 bick 22 0 r2 32 bick 23 23 256 bick lrck (mode27) figure 35. mode 22/27 timing (tdm256 mode) bick(256fs) sdto1(o) sdti1(i) 22 0 l1 32 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 l4 32 bick 22 0 r4 32 bick 22 0 r1 32 bick 22 23 23 23 23 23 23 23 23 23 23 23 23 lrck (mode23) 22 22 0 l2 32 bick 22 0 r2 32 bick 23 23 256 bick lrck (mode28) figure 36. mode 23/28 timing (tdm256 mode)
[ak4611] ms1050-e-02 2010/06 - 39 - bick(256fs) sdto1(o) sdti1(i) 23 0 l1 32 bick 23 0 l1 32 bick 23 0 r1 32 bick 23 0 l2 32 bick 23 0 r2 32 bick 23 0 l3 32 bick 23 0 r3 32 bick 23 0 l4 32 bick 23 0 r4 32 bick 23 0 r1 32 bick 23 lrck (mode24) 23 32 bick 32 bick 23 0 l2 23 0 r2 256 bick lrck (mode29) figure 37. mode 24/29 timing (tdm256 mode) bick(128fs) sdto1(o) 22 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 22 0 r1 32 bick 22 23 23 sdti1(i) 0 0 14 0 14 0 15 15 15 15 lrck (mode30) sdti2(i) 0 0 0 14 0 15 15 15 14 15 15 14 14 14 15 23 14 22 0 l2 32 bick 22 0 r2 32 bick 23 23 128 bick lrck (mode35) figure 38. mode 30/35 timing (tdm128 mode)
[ak4611] ms1050-e-02 2010/06 - 40 - bick(128fs) sdto1(o) 22 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 22 0 r1 32 bick 22 23 23 sdti1(i) 0 0 18 0 18 0 19 19 19 19 lrck (mode31) sdti2(i) 0 0 0 18 0 19 19 19 18 19 19 18 18 18 19 23 18 22 0 l2 32 bick 22 0 r2 32 bick 23 23 128 bick lrck (mode36) figure 39. mode 31/36 timing (tdm128 mode) bick(128fs) sdto1(o) 22 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 22 0 r1 32 bick 22 23 23 sdti1(i) 0 0 22 0 22 0 23 23 23 23 lrck (mode32) sdti2(i) 0 0 0 22 0 23 23 23 22 23 23 22 22 22 23 23 22 22 0 l2 32 bick 22 0 r2 32 bick 23 23 128 bick lrck (mode37) figure 40. mode 32/37 timing (tdm128 mode)
[ak4611] ms1050-e-02 2010/06 - 41 - bick(128fs) sdto1(o) 22 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 22 0 r1 32 bick 22 23 23 sdti1(i) 0 0 22 0 22 0 23 23 23 lrck (mode33) sdti2(i) 23 22 22 23 22 23 0 0 22 0 22 0 23 23 23 23 22 22 22 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 128 bick lrck (mode38) figure 41. mode 33/38 timing (tdm128 mode) bick(128fs) sdto1(o) 22 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 23 0 r1 32 bick 23 sdti1(i) 0 0 23 0 23 0 lrck (mode34) sdti2(i) 23 23 23 0 0 23 0 23 0 23 23 23 23 0 l2 32 bick 23 0 r2 32 bick 128 bick lrck (mode39) figure 42. mode 34/39 timing (tdm128 mode)
[ak4611] ms1050-e-02 2010/06 - 42 - overflow detection the ak4611 has an overflow detect function for the analog input. the overflow detect function is enabled when the ovfe bit is set to ?1?. overflow detec tion is applied to the analog input of each channel, and the result is or?d. ovf1/2 pins goes to ?h? according to the group set by ovfm2-0 bits, if analog input of lch or rch overflows (more than -0.3dbfs). when the analog input is overflowed, the output signal of ovf1/2 pins have the same group delay as adc (gd = 16/fs = 333 s @fs=48khz). ovf1/2 pins are ?l? for 518/fs (=11.8ms @fs=48khz) after pdn = ? ?, and then overflow detection is enabled. mode ovfm2 ovfm1 ovfm0 lin1 or rin1 lin2 or rin2 0 0 0 0 ovf1 ovf1 1 0 0 1 ovf1 ovf2 2 0 1 0 - ovf1 3 0 1 1 ovf2 - 4 1 0 0 ovf2 ovf2 5 1 0 1 6 1 1 0 7 1 1 1 disable (ovf2=ovf1= ?l?) (default) table 15. overflow detect control (ovfe bit = ?1?) zero detection the ak4611 has two pins for zero detect flag outputs. zero detect function is enabled when the ovfe bit is set to ?0?. channel grouping can be selected by the dzfm3-0 bits. ( table 16 ) the dzf1 pin corresponds to the group 1 channels and the dzf2 pin corresponds to the group 2 channels. dzf1 is and operation of all eight channels and dzf2 is disabled (?l?) at mode 0, ?h? at mode 1-3. when the input data of all channels in the group 1(group 2) are continuously zeros for 8192 lrck cycles, the dzf1 (dzf2) pin goes to ?h?. the dzf1 (dzf2) pin immediately returns to ?l? if input data of any channels in the group 1(group 2) is not zero. dzfm aout mode 3 2 1 0 l1 r1 l2 r2 l3 r3 l4 r4 0 0 0 0 0 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 1 0 0 0 1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 2 0 0 1 0 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 3 0 0 1 1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 4 0 1 0 0 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 5 0 1 0 1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf2 6 0 1 1 0 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf2 dzf2 7 0 1 1 1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf2 dzf2 dzf2 8 1 0 0 0 dzf1 dzf1 dzf1 dzf1 dzf2 dzf2 dzf2 dzf2 9 1 0 0 1 dzf1 dzf1 dzf1 dzf2 dzf2 dzf2 dzf2 dzf2 10 1 0 1 0 dzf1 dzf1 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 11 1 0 1 1 dzf1 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 12 1 1 0 0 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 13 1 1 0 1 14 1 1 1 0 disable (dzf1=dzf2= ?l?) 15 1 1 1 1 (default) table 16. zero detect control (ovfe bit = ?0?)
[ak4611] ms1050-e-02 2010/06 - 43 - digital attenuator ak4611 has a channel-independent digital attenuator (256 leve ls, 0.5db steps). attenuation level of each channel can be set by each the att7-0 bits ( table 17 ). att7-0 attenuation level 00h 0db 01h -0.5db 02h -1.0db : : 7dh -62.5db 7eh -63.0db 7fh -63.5db : feh -127.0db ffh mute (- ) (default) table 17. attenuation level of digital attenuator transition time between set values of att7-0 b its can be selected by the ats1-0 bits ( table 18 ). transition between set values is the soft transition in mode1/2/3 e liminating switching noise in the transition. mode ats1 ats0 att speed 0 0 0 4096/fs 1 0 1 2048/fs 2 1 0 512/fs 3 1 1 256/fs (default) table 18. transition time between set values of att7-0 bits the transition between set values is a soft transition of 4096 levels in mode 0. it takes 4096/fs (85.3ms@fs=48khz) from 00h(0db) to ffh(mute). if th e pdn pin goes to ?l?, the atts are initialized to 00h. the atts also become 00h when rstn bit = ?0?, and fade to their current value when rstn bit returns to ?1?.
[ak4611] ms1050-e-02 2010/06 - 44 - soft mute operation soft mute operation is performed in the digital domain. when the smute bit becomes ?1?, the output signal is attenuated to - in the cycle set by ats bits ( table 18 ) from the current att level. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level in the cycle set by ats bits. if the soft mute is cancelled before attenuating to - after starting the operation, attenuation is discontinued and it is returned to att level by the same cycle. soft mute is effective for changing the signal source without stopping the signal transmission. smute bit attenuation dzf1,2 att level - aout 8192/fs gd gd (1) (3) (4) (5) (2) notes: (1) the time for input data attenuation to - ( table 18 ). for example, in normal speed mode, this time is 4096lrck cycles (4096/fs) at att_data=00h. att trans ition of the soft-mute is from 00h to ffh (2) the time for input data recovery to att level ( table 18 ). for example, in normal speed mode, this time is 4096lrck cycles (4096/fs) at att-data=ffh. a tt transition of soft-mute is from ffh to 00h. (3) the analog output corresponding to the digital input has group delay, gd. (4) if the soft mute is cancelled before attenuating to - , the attenuation is discontinued and returned to att level by the same cycle. (5) when the input data at all the channels of the group ar e continuously zeros for 8192 lrck cycles, dzf1, 2 pins of each channel goes to ?h?. dzf1/2 pins immediately returns to ?l? if the input data of eith er channel of the group are not zero after going ?h?. figure 43. soft mute and zero detection system reset the ak4611 should be reset once by bringing the pdn pin = ?l? upon power-up. the ak4611 is powered up and the internal timing starts clocking by lrck ? ? after exiting the power down state of reference voltage (such as vcom) by mclk. the ak4611 is in power-down mode until mclk and lrck are input.
[ak4611] ms1050-e-02 2010/06 - 45 - power-down all adcs and dacs of the ak 4611 are placed in power-down mode by brin ging the pdn pin ?l? which resets both digital filters at the same time. the pdn pin ?l? also resets the control registers to their default values. in power-down mode, when the dvmpd pin ?l?, the analog outputs go to vcom voltage, when the dvmpd pin =?h?, the analog outputs go to hi-z. the sdto1-2, dzf1-2 pins go to ?l? in the power-dwon mode. this reset should always be executed after power-up. for the adc, an analog initialization cycl e (518/fs) starts 3~4/fs afte r exiting power-down mode. the output data, sdto1-2, is availa ble after 521~522 cycles of the lrck clock. for the dac, an analog initialization cycle (516/fs) starts 3~4/fs after exiting power-down mode. the analog outputs are vcom vo ltage when the dvmpd =pin ?l?, and the analog outputs go to hi-z when the dvmpd pin =?h? during the initialization. figure 44 shows the power-down and power-up sequences. a dc internal state pd n cl ock in mclk,lrck,sclk a dc in (analog) a dc out (digital) dac internal state dac in (di gi tal ) dac out (anal og) external mute mut e on (9) power power-down don ?t care gd ?0?data power-down ?0?data gd (3) (3) (4) (7) (7) 518/fs init cycle normal op era tion (1) gd normal op era tion gd (6) (7) 516/fs init cycle (2) mut e on ?0?data ?0?data d on?t care 3~4/fs (10) (5) dzf1/dzf2 don?t care (7) 10~11/fs (11) (12) notes: (1) the analog part of adc is initia lized after exiting power-down state. (2) the analog part of dac is initia lized after exiting power-down state. (3) digital output corresponds to analog input and analog output corresponds to digital input have group delay (gd). (4) adc output is ?0? data at power-down state. (5) the analog outputs are vcom voltage when the dvmpd pin ?l?, and the analog outputs go to hi-z when the dvmpd pin ?h? in power-down mode. (6) click noise occurs at the end of initialization of the analog part. mute the digital output externally if the click noise influences system applications. (7) click noise occurs at the falling edge of pdn and at 519~520/fs after the rising edge of the pdn pin. (8) dzf1-2 pins are ?l? in power-down mode (pdn pin = ?l?). (9) please mute the analog output externally if the click noise (7) influences system applications. (10) there is a delay, 3~4/fs from pdn pin ?h? to the start of initial cycle. (11) dzf pin= ?l? for 10 11/fs after pdn pin = ? ?. (12) the pdn pin must be ?l? when power up the ak4611 and set to ?h? after all poweres are supplied. figure 44. pin power-down/pin power-up sequence example
[ak4611] ms1050-e-02 2010/06 - 46 - all adcs and all dacs can be powered-down individually th rough the pmadc bits and pmdac bits, when the pmvr bit ?1?. adc1-2 can be power-down individually through the pmad2-1 bits. dac1-4 can be power-down individually by pmda4-1 bits. in this case, the internal register values are not initialized. when pmadc bit = ?0?, sdto1-2 goes to ?l?. when pmdac bit = ?0?, the analog outputs go to vc om voltage when the dvmpd pi n is ?l?, and the analog outputs go to hi-z when the dvmpd pin ?h?. when pmdac bit = ?0?, dzf1-2 pins go to ?h?. as some click noise occurs, the analog output should be muted externally if the click noise influences system applications. figure 45 shows the power-down and power-up sequences. a dc internal state pmadc/pmdac bit 518/fs normal operation power-down init cycle normal operation (1) don?t care gd gd clock in mclk,lrck,sclk a dc in (analog) ?0?data a dc out (digital) normal operation power-down normal operation dac internal state ?0?data dac in (digital) dac out (analog) gd external mute mute on gd (3) (3) (4) (6) (7) (7) (9) 516/fs init cycle (2) (8) 8 9/fs (12) (5) 3~4/fs (11) 4~5/fs (10) pmvr bit dzf1/dzf2 notes: (1) the analog section of adc is in itialized after exiting power-down state. (2) the analog section of dac is in itialized after exiting power-down state. (3) digital output corresponding to the analog inputs and analog outputs corresponding to the digital inputs have group delay (gd). (4) adc output is ?0? data at power-down state. (5) the analog outputs are vcom voltage when the dvmpd pin ?l?, and the analog outputs go to hi-z when the dvmpd pin ?h? in power-down mode. (6) click noise occurs at the end of initialization of the analog part. mute the digital output externally if the click noise influences system application. (7) click noise occurs at 4 5/fs after pmdac bit becomes ?0?, and occurs at 519 520/fs after pmdac bit becomes ?1?. (8) dzf1-2 pins are ?h? in power-down mode (pmdac bit = ?0?). (9) mute the analog output externally if the click noise (7) influences system application. (10) there is a delay, 4~5/fs from pmdac bit becomes ?0? to the app licable adc power-down. there is a delay, 4~5/fs from pmdac bit becomes ?0? to the applicable dac power-down. (11) there is a delay, 3~4/fs from pmadc and pmdac bits become ?1? to the start of initial cycle. (12) dzf pin= ?l? for 8 9/fs after pmdac bit becomes ?1?. figure 45. bit power-down/bit power-up sequence example
[ak4611] ms1050-e-02 2010/06 - 47 - reset function when rstn bit= ?0?, the analog and digital part of adc and the digital part of dacs are powered-down, but the internal register are not initialized. the analog outputs go to vcom voltage regardless of the dvmpd pin setting, then dzf1-2 pins go to ?h? and sdto1-2 pins go to ?l?. as some click noise occurs, the analog output should be muted externally if the click noise influences system application. figure 46 shows the power-up sequence. a dc internal state rstn bit normal operation power-down normal operation don?t care gd gd clock in mclk,lrck,sclk a dc in (analog) ?0?data a dc out (digital) normal operation normal operation dac internal state ?0?data dac in (digital) dac out (analog) gd gd (2) (2) (3) (4) (6) (6) dzf1/dzf2 internal rstn bit digital block power-down 3~4/fs (9) 4~5/fs (8) 8 9/fs (7) (5) 518/fs init cycle (1) notes: (1) the analog section of the adc is initialized after exiting reset state. (2) digital output corresponding to the analog inputs, and analog outputs corresponding to the digital inputs have group delay (gd). (3) adc output is ?0? data at power-down state. (4) click noise occurs when the internal rstn bit becomes ?1?. mute the digital output externally if the click noise influences system application. (5) the analog outputs go to vcom voltage regardless of the dvmpd pin setting when rstn bit becomes ?0?. (6) click noise occurs at 4 5/fs after rstn bit becomes ?0?, and occurs at 3 4/fs after rstn bit becomes ?1?. (7) dzf pins go to ?h? when the rstn bit becomes ?0?, and go to ?l? at 8~9/fs after rstn bit becomes ?1?. (8) there is a delay, 4~5/fs from rstn bit ?0? to the internal rstn bit ?0?. (9) there is a delay, 3~4/fs from rstn bit ?1? to the start of initial cycle. figure 46. reset sequence example
[ak4611] ms1050-e-02 2010/06 - 48 - adc partial power-down function all of the adcs can be powered-down individually by pmad2- 1 bits. the analog section and the digital section of the adc are in power-down mode when the pm ad2-1 bits = ?0?. the analog section of adcs are initialized after exiting the power-down state. digital output corresponding to analog input have group delay (gd). adc output is ?0? data at the power-down state. click noise occurs when the internal rstn bit becomes ?1?. mute the digital output externally if the click noise influences system applications. figure 47 shows the power-down and power-up sequences by pmad2-1 bits. pmad2-1 bit a dcdigital internal state normal operat ion a dc analog internal state power-down clock in mclk,lrck,sclk normal operation channel power-down normal operat ion power down channel normal operation power-down power-down normal operation 2~3/f s (2) 2~3/fs (2) init cycle normal operation 518/fs (3) init cycle normal operation 518/fs (3) 4~5/fs (1) 4~5/f s (1) gd gd a dc in (analog) ?0?data a dc out (digital) (4 ) (5) (6 ) (6) (4 ) gd gd a dc in (analog) ?0?data a dc ou t (digital) (5) (4 ) (4 ) notes. (1) there is a delay, 4~5/fs from pmad2-1 bits become ?0? to the applicable adc power-down. (2) there is a delay, 2~3/fs from pmad2-1 bits ?1? to the start of initial cycle. (3) the analog section of the adc is initialized after exiting reset state. (4) analog output corresponding to the digital inputs have group delay (gd). (5) adc output is ?0? data at power-down state. (6) click noise occurs when the internal rstn bit becomes ?1?. mute the digital output externally if the click noise influences system application. figure 47. adc partial power-down example
[ak4611] ms1050-e-02 2010/06 - 49 - dac partial power-down function all of the dacs can be powered-down individually by pmda4- 1 bits. the analog section and the digital section of the dac are placed in power-down mode when the pmda4-1 bits = ?0?. the analog output of the powered-down channels, which is by pmda4-1 bits, go to the voltage of vcom when the dvmpd pin is ?l?, and go to hi-z when the dvmpd pin ?h?. although dzf detection is in operation, the ak4611 stops reflecting the result of dzf detection to dzf1-2 pins. some click noise occurs in both set-up and release of power-down. mute the analog output externally or set pmda4-1 bits when pmdac bit = ?0? or rstn bit = ?0?, if click noise aversely affects system performance. figure 48 shows the sequence of the power-down and the power-up by pmda4-1 bits. pmda4-1 bit dzf1/dzf2 8192/fs ?0?dat a dac in (digital) dac out (analog) gd gd (1 ) (3 ) (3) (2) dac digital internal state normal operation dac analog internal state power-down clock in mclk,lrck,sclk dac in (digital) dac out (analog) normal operation channel (7) (8 ) gd 8192/fs gd power-down normal operat ion (2 ) (3) (3) (7) power down channel dzf detect internal state dzf detect internal state ?0?data (9) normal operation power-down power-down normal operation 2~3/f s (5) 2~3/fs (5) init cycle normal operation 516/fs (6) init cycle normal operation 516/fs (6) 4~5/fs (4) 4~5/f s (4) notes: (1) digital output corresponding to the analog inputs, and analog outputs corresponding to the digital inputs have group delay (gd). (2) analog output of the dac powered down by pmda4-1 = ?0? and goes to vcom voltage when the dvmpd pin =?l?, and the analog outputs go to hi-z when the dvmpd pin =?h?. (3) click noise occurs at 4 5/fs after rstn bit becomes ?0?, and occurs at 3 4/fs after rstn bit becomes ?1?. after pmda4-1 bits are changed, some click noise occurs immediately at output of the channel changed by the own pd bits. (4) the dacs will be powered-down 4~5fs after pmda4-1 bits = ?0? (5) the initiation stars 2~3fs after pmda4-1 bits are set to ?1?. (6) the analog parts of dacs are initilised after exiting power down mode. (7) although dzf detection is active at a certain channe l set up though pmda4-1 = ?0?, the ak4611 stops reflecting the result of dzf detection to dzf1-2 pins. (8) dzf detection of the dac which is set up by the powe r-down setting is ignored, and dzf1-2 pins go to ?h?. (9) when signal is input to a dac, even if the partical pow er down is applied, dzf1-2 pins will not become ?h?. figure 48. dac partial power-down example
[ak4611] ms1050-e-02 2010/06 - 50 - serial control interface the ak4611?s functions are controlled through registers. the registers may be written by two types of control modes. the chip address is determined by the state of the cad0 an d cad1 inputs. the pdn pin = ?l? initializes the registers to their default values. writing ?0? to the rstn bit can initialize th e internal timing circuit, but the register data will not be initialized. (1) 4-wire serial control mode (i2c pin = ?l?) the internal registers may be written through the 4-wire p interface pins (csn, cclk, cd ti and cdto). the data on this interface consists of a 2- bit chip address, read/write, register addre ss (msb first, 5bits) and control data (msb first, 8bits). the chip address high bit is fixed to ?1? and the lower bit is set by the cad0 pin. address and data are clocked in on the rising edge of cclk and data is clocked out on the falling edge. after a low-to-high transition of csn, data is latched for write operations and cdto bit outputs hi-z. the clock speed of cclk is 5mhz (max). the value of internal registers is initialized when the pdn pin = ?l?. cdti cclk csn c1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 cdto hi-z write cdti c1 a1 a2 a3 a4 r/w c0 a0 cdto hi-z read d4 d5 d6 d7 d0 d1 d2 d3 hi-z ?h? or ?l? ?h? or ?l? ?h? or ?l? ?h? or ?l? ?h? or ?l? ?h? or ?l? c1 ? c0: chip addres s (c1=cad1, c0=ca0) r/w: read / write (?1?: write, ?0?: read) a4 - a0: register address d7 ? d0: control data figure 49. serial control i/f timing
[ak4611] ms1050-e-02 2010/06 - 51 - (2) i 2 c-bus control mode (i2c pin = ?h?) the ak4611 supports the fast-mode i 2 c-bus (max: 400khz). (2)-1. write operations figure 50 shows the data transfer sequence of the i 2 c-bus mode. all commands are pr eceded by start condition. a high to low transition on the sda line while scl is high indicates start condition ( figure 56 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant five bits of the slave address are fixed as ?00100?. the next bits are cad1 and cad0 (device address bit). this bit identifies the specific device on the bus . the hard-wired input pins (cad1/0 pins) set these device address bits ( figure 51 ). if the slave address matches that of the ak4611, the ak4611 generates an acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 57 ). r/w bit = ?1? indicates that the read operation is to be executed. ?0? indicates that the write operation is to be executed. the second byte consists of the contro l register address of the ak4611. the fo rmat is msb first, and those most significant 3-bits are fixed to zeros ( figure 52 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 53 ). the ak4611 generates an acknowledge after each byte is received. data transfer is always terminated by stop condition generated by the master. a low to high transition on the sda line while scl is high defines stop condition ( figure 56 ). the ak4611 can perform more than one by te write operation per sequence. after receipt of the thir d byte the ak4611 generates an acknowledge and awaits the ne xt data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after r eceiving each data packet the inte rnal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the cloc k signal on the scl line is low ( figure 58 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 50. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 cad1 cad0 r/w (those cad1/0 should match with cad1/0 pins) figure 51. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 52. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 53. byte structure after the second byte
[ak4611] ms1050-e-02 2010/06 - 52 - (2)-2. read operations set the r/w bit = ?1? for the read opera tion of the ak4611. after transmission of data, the master can read the next address?s data by generating an acknowledg e instead of terminating the write cycle af ter the receipt of the first data word. after receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. the ak4611 supports two basic read operations: current address read and random address read. (2)-2-1. curren t address read the ak4611 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address ?n?, the next current read operation would access data from the address ?n+1?. afte r receipt of the slave address with r/w bit ?1?, the ak4611 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak4611 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) n a c k p s t o p data(n) m a s t e r m a s t e r m a s t e r m a s t e r m a s t e r figure 54. current address read (2)-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing a slave address with the r/w bit =?1?, the master must ex ecute a ?dummy? write operatio n first. the master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register addres s is acknowledged , the master immediately reissues the start request and the slave address with the r/w bit =?1?. the ak4611 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak4611 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r figure 55. random address read
[ak4611] ms1050-e-02 2010/06 - 53 - scl sda stop condition start condition s p figure 56. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 57. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 58. bit transfer on the i 2 c-bus
[ak4611] ms1050-e-02 2010/06 - 54 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 0 0 0 pmvr pmadc pmdac rstn 01h power management 2 0 0 0 0 0 1 pmad2 pmad1 02h power management 3 0 0 1 1 pmda4 pmda3 pmda2 pmda1 03h control 1 tdm1 tdm0 dif2 dif1 dif0 ats1 ats0 smute 04h control 2 0 mcko cks1 cks0 dfs1 dfs0 acks div 05h de-emphasis1 dem41 dem40 d em31 dem30 dem21 dem20 dem11 dem10 06h reserved 0 0 0 0 0 1 0 1 07h overflow detect 0 0 0 0 ovfe ovfm2 ovfm1 ovfm0 08h zero detect loop1 loop 0 0 0 dzfm3 dzfm2 dzfm1 dzfm0 09h input control 0 0 0 0 0 1 die2 die1 0ah output control 0 0 1 1 doe4 doe3 doe2 doe1 0bh lout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 0ch rout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 0dh lout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 0eh rout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 0fh lout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 10h rout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 11h lout4 volume control att7 att6 att5 att4 att3 att2 att1 att0 12h rout4 volume control att7 att6 att5 att4 att3 att2 att1 att0 note: for addresses from 13h to 1fh, data is not written. when the pdn pin goes to ?l?, the regist ers are initialized to their default values. when rstn bit goes to ?0?, the internal timing is rese t and the dzf1-2 pins go to ?h?, but registers are not initialized to their default values.
[ak4611] ms1050-e-02 2010/06 - 55 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 0 0 0 pmvr pmadc pmdac rstn r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 1 1 1 1 rstn: internal timing reset 0: reset. dzf1-2 pins go to ?h?, but registers are not initialized. 1: normal operation pmdac: power management of dac1-4 0: power-down 1: normal operation pmadc: power management of adc1-2 0: power-down 1: normal operation pwvr: power management of reference voltage 0: power-down 1: normal operation when any blocks are powered-up, the pmvr bit must be set to ?1?. pmvr bit can be set to ?0? only when pmadal=pmadar= bits = ?0?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 0 0 0 0 0 1 pmad2 pmad1 r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 1 1 1 pmad2-1: power management of adc1-2 (0: power-down, 1: normal operation) pmad1: power management control of adc1 pmad2: power management control of adc2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h power management 3 0 0 1 1 pmda4 pmda3 pmda2 pmda1 r/w rd rd rd rd r/w r/w r/w r/w default 0 0 1 1 1 1 1 1 pmda4-1: power management of dac1-4 (0: power-down, 1: normal operation) pmda1: power management control of dac1 pmda2: power management control of dac2 pmda3: power management control of dac3 pmda4: power management control of dac4
[ak4611] ms1050-e-02 2010/06 - 56 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h control 1 tdm1 tdm0 dif2 dif1 dif0 ats1 ats0 smute r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 1 0 0 0 0 0 smute: soft mute enable 0: normal operation 1: all dac outputs soft-muted ats1-0: digital attenuator transition time setting ( table 18 ) initial: ?00?, mode 0 dif2-0: audio data interface modes ( table 11 , table 12 , table 13 , table 14 ) initial: ?100?, mode 4 tdm1-0: tdm format select ( table 11 , table 12 , table 13 , table 14 ) mode tdm1 tdm0 sdti sampling speed 0 0 0 1-6 stereo mode (normal, double, quad speed mode) 1 0 1 1 tdm512 mode (normal speed mode) 2 1 1 1-2 tdm256 mode (double speed mode) 3 0 1 1-3 tdm128 mode (quad speed mode) addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h control 2 0 mcko cks1 cks0 dfs1 dfs0 acks div r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 1 0 0 0 0 0 div: output of master clock frequency 0: x 1 1: x 1/2 acks: master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected automatically at acks bit ?1?. in this case, the setting of dfs are ignored. when this bit is ?0?, dfs0, 1 set the sampling speed mode. dfs1-0: sampling speed mode ( table 1 ) the setting of dfs is ignored at acks bit =?1?. cks1-0: master clock input frequency select ( table 2 ) mcko: master clock output enable 0: output ?l? 1: output ?mcko?
[ak4611] ms1050-e-02 2010/06 - 57 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h de-emphasis1 dem41 dem40 dem31 dem30 dem21 dem20 dem11 dem10 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 1 0 1 0 1 dema11-10: de-emphasis response control for dac1 data on sdti1 ( table 8 ) initial: ?01?, off dema21-20: de-emphasis response control for dac2 data on sdti1 ( table 8 ) initial: ?01?, off dema31-30: de-emphasis response control for dac3 data on sdti1 ( table 8 ) initial: ?01?, off dema41-40: de-emphasis response control for dac4 data on sdti1 ( table 8 ) initial: ?01?, off addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h overflow detect 0 0 0 0 ovfe ovfm2 ovfm1 ovfm0 r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 0 1 1 1 ovfm2-0: overflow detect mode select ( table 15 ) initial: ?111?, disable ovfe: overflow detection enable ( table 15 ) 0: disable, pin#33 becomes dzf2 pin. 1: enable, pin#33 becomes ovf pin.
[ak4611] ms1050-e-02 2010/06 - 58 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h zero detect loop1 loop0 0 0 dzfm3 dzfm2 dzfm1 dzfm0 r/w r/w r/w rd rd r/w r/w r/w r/w default 0 0 0 0 1 1 1 1 dzfm3-0: zero detect mode select ( table 16 ) initial: ?1111?, disable loop1-0: loopback mode enable 00: normal (no loop back) 01: lin1 lout1, lout2 rin1 rout1, rout2 lin2 lout3, lout4 rin2 rout3, rout4 the digital adc output is connected to the digital dac input. in this mode, the input dac data to sdti1-4 are ignored. the audio format of sdto at loopback mode becomes mode 3 at mode 0 or 1, and mode 5 at mode 2, respectively. 10: sdti1(l) sdti2(l), sdti3(l), sdti4(l) sdti1(r) sdti2(r), sdti3(r), sdti4(r) in this mode, the input dac data to sdti2-4 are ignored. 11: not available loop1-0 should be set to ?00? at tdm mode. addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h output control 0 0 0 0 0 1 die2 die1 r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 1 1 1 die2-1: adc1-2 differential i nput enable (0: single-end input, 1: differential input) die1: adc1 differential input enable die2: adc2 differential input enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah output control 0 0 1 1 doe4 doe3 doe2 doe1 r/w rd rd rd rd r/w r/w r/w r/w default 0 0 1 1 1 1 1 1 doe4-1: dac1-4 differential output enable (0 : single-end input, 1: differential input) doe1: dac1 differential output enable doe2: dac2 differential output enable doe3: dac3 differential output enable doe4: dac4 differential output enable
[ak4611] ms1050-e-02 2010/06 - 59 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh lout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 0ch rout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 0dh lout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 0eh rout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 0fh lout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 10h rout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 11h lout4 volume control att7 att6 att5 att4 att3 att2 att1 att0 12h rout4 volume control att7 att6 att5 att4 att3 att2 att1 att0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 att7-0: attenuation level ( table 17 )
[ak4611] ms1050-e-02 2010/06 - 60 - system design condition: differential input (die2-1 bit = ?11? ), differential output (doe4-1 bit = ?1111?) 4-wire serial control interface (i2c pin = ?l?) master mode (m/s pin = ?h?) the ak4611 has the analog anti-alias filter for differential input. the ak4611 does not have the analog smoothing filter for differential output. ak4611 lout4+ 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 lout2- rout2+ rout2- lout3+ lout3- rout3+ rout3- vss2 avdd2 vrefh2 lout4-1 rout4+ rout4- tst9 tst10 tst11 tst12 tst13 tst14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 tst4 tst5 cad0 i2c cclk / scl cdti / sda cdto tst1 tst3 nc xto cad1 csn tvdd2 vss3 dvdd mcko m/s tst2 pdn lout2+ 4 0 39 38 3 7 36 35 3 4 33 3 2 3 1 29 2 8 30 27 2 5 24 2 6 2 3 22 21 rout1- rout1+- lout1+ dvmpd lout1- tst8 tst7 sdti4 sdti3 sdti2 bick lrck sdti1 tst6 sdto2 sdto1 vss4 tvdd1 xti / mclk 6 1 6 2 63 6 4 65 66 6 7 68 69 70 72 7 3 71 74 76 77 7 5 7 8 7 9 80 tst15 tst16 ovf1 / dzf1 lin1- rin1+ rin1- lin2+ lin2- rin2+ tst17 tst18 rin2- vss1 vrefh1 vcom tst19 tst20 ovf2 / dzf2 lin1+ a vdd1 mute lpf mute lpf mute lpf mute lpf mute lpf 1.6v to 3.6v digital c1 c1 analog 3.3v analo g 3.3v + 2.2u 0.1u + + + + + 1.6v to 3.6v di g ital 1.8v di g ital core dsp p analo g ground di g ital ground 0.1u 10u 10u 10u 0.1u 0.1u 0.1u 10u 10u 0.1u mute lpf mute lpf mute lpf figure 59. typical connection diagram1
[ak4611] ms1050-e-02 2010/06 - 61 - condition: single-end input (die2-1 bit = ?00?), single-end output (doe4-1 bit = ?0000?) i 2 c bus control interface (i2c pin = ?h?) slave mode (m/s pin = ?l?) the ak4611 has the analog anti-alias filter for single-ended input. the ak4611 has the analog smoothing filter for single-ended output. ak4611 lout4 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 lout2- rout2 rout2- lout3 lout3- rout3 rout3- vss2 avdd2 vrefh2 lout4- rout4 rout4- tst9 tst10 tst11 tst12 tst13 tst14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 tst4 tst5 cad0 i2c cclk / scl cdti / sda cdto tst1 tst3 nc xto cad1 csn tvdd2 vss3 dvdd mcko m/s tst2 pdn lout2 4 0 39 38 3 7 36 35 34 33 3 2 3 1 2 9 2 8 30 27 2 5 24 2 6 2 3 22 21 rout1- rout1 lout1 dvmpd lout1- tst8 tst7 sdti4 sdti3 sdti2 bick lrck sdti1 tst6 sdto2 sdto1 vss4 tvdd1 xti / mclk 6 1 62 63 6 4 65 66 6 7 68 69 7 0 72 7 3 71 74 7 6 77 7 5 78 7 9 80 tst15 ovf1 / dzf1 lin1- rin1 rin1- lin2 lin2- rin2 tst17 tst18 rin2- vss1 vrefh1 vcom tst19 tst20 ovf2 / dzf2 lin1 a vdd1 tst16 mute mute 1.6v to 3.6v digital analog 3.3v analo g 3.3v + 2.2u 0.1u + + + + + 1.6v to 3.6v di g ital 1.8v di g ital core dsp p analo g ground di g ital ground mute mute mute mute 10u 0.1u 0.1u 0.1u 10u 10u 0.1u 10u 10u 0.1u mute mute figure 60. typical connection diagram2
[ak4611] ms1050-e-02 2010/06 - 62 - 1. grounding and power supply decoupling the ak4611 requires careful attention to power supply and grounding arrangements. avdd1, avdd2, tvdd1 and tvdd2 are usually supplied from analog supply in system. alternatively if avdd1, avdd2, tvdd1 and tvdd2 are supplied separately, the power up sequence is not critical. vss1, vss2, vss3 and vss4 of the ak4611 must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4611 as possible, with the small value cer amic capacitor being the nearest. 2. voltage reference inputs the voltage of vrefh1, vrefh2 set the analog input/output range. the vrefh1 pin is normally connected to avdd1 with a 0.1f ceramic capacitor. the vr efh2 pin is normally connected to avdd2 with a 0.1f ceramic capacitor. vcom is a signal ground of this chip and output the voltage avdd1x1/2. an electrolytic capacitor 2.2f parallel with a 0.1f ceramic capacitor attached to the vcom pin eliminates the effects of high freque ncy noise. ceramic capacitors should be as near to the pin as possible. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vrefh1, vrefh2 and vcom pins in order to avoid unwanted coupling into the ak4611. 3. analog inputs the adc inputs correspond to single-ende d and differential are able to select by die2-1 bits. when the inputs are single-ended, internally biased to the common voltage (avdd1x1/2) with 9k (typ) resistance. the input signal range scales with the supply voltage and nominally 0.65xvrefh1 vpp (typ) @fs=48khz. when the inputs are differential, internally biased to the common voltage (avdd2x1/2) with 13k (typ) resistance. the input signal range between lin(rin)+ and lin(rin) ? scales with the supply voltage and nominally 0.65xvrefh1 vpp (typ) @fs=48khz the adc output data format is 2?s complement. the internal hpf removes the dc offset. the ak4611 samples the analog inputs at 128fs (@ fs=48khz). the digital filter rejects noise above the stop band except for multiples of the sampling frequency of analog inputs. the ak4611 includes an anti-aliasing filter (rc filter) to attenuate a noise around the sampling frequency of analog inputs. 4. analog outputs the dac outputs correspond to single-ended and differential ar e able to select by doe4-1 bits. when the outputs are single-ended, the output signal range is centered around the vcom voltage and nominally 0.63 x vrefh2 vpp. when the outputs are differential, the output signal ranges are 0.63 x vrefh2 vpp (typ) centered around the vcom voltage. the differential outputs are summed externally, v aout = [l(r)out+]-[l(r)out-] between l(r)out+ and l(r)out-. if the summing gain is 1, the output range is 4.16vpp (typ@avdd2=3.3v). the bias voltage of the external summing circuit is supplied externally. the dac input data format is 2?s complement. the output voltage is a positive full scale for 7fffffh(@24bit) and a negative full scale for 800000h (@24bit). the ideal output is vcom voltage for 000000h(@24bit). the internal analog filters remove most of the noise generated by the delta-sigma modulator of dac beyond the audio passband, when the single-end input mode. the differential output mode does not have the internal analog filters, therefore this noise should be remove by the external analog filters. dc offsets on analog outputs are eliminated by ac coupling since dac outputs have dc offsets of a few mv.
[ak4611] ms1050-e-02 2010/06 - 63 - 5. external analog inputs circuit figure 61 shows the input buffer circuit example 1. the input level of this circuit is 4.3vpp (ak4611: typ. 2.15vpp). 4.3vpp analog in 22 10k 5.1k vp+ vp- njm5532 vp+ = +12v vp- = -12v 4.7k 4.7k njm5532 bias bias 10 0.1 bias 10k 10k va va = +3.3v ain+ ak4611 2.15vpp ain- figure 61. input buffer circuit exam ple 1 (dc coupled single-end input) figure 62 shows the input buffer circuit example 2. the input level of this circuit is 4.3vpp (ak4611: typ. 2.15vpp). 4.3vpp analog in 22 10k 5.1k vp+ vp- njm5532 vp+ = +12v vp- = -12v 4.7k 4.7k njm5532 10 ain+ ak4611 2.15vpp 10 2.15vpp ain- figure 62. input buffer circuit exam ple 2 (ac coupled single-end input) figure 63 shows the input buffer circuit example 3. the input level of this circuit is 2.15vpp (ak4611: typ. 2.15vpp). analog in analog in 2.15vpp 2.15vpp 10 10 ain+ ain- ak4611 figure 63. input buffer circuit example 3 (ac coupled differential input)
[ak4611] ms1050-e-02 2010/06 - 64 - figure 64 shows the input buffer circuit example 4. the input level of this circuit is 2.15vpp (ak4611: typ. 2.15vpp). analog in 2.15vpp 10 ain+ ain- ak4611 open figure 64. input buffer circuit exam ple 4 (ac coupled single-end input) 6. external analog outputs circuit figure 65 shows the output buffer circuit example 1. the output level of this circuit is 4.16vpp (ak4611: typ. 2.08vpp). 4.7k vp+ = +12v vp- = -12v r1 4.7k aout- ak4611 aout+ 4.16vpp analog out 2.08vpp 2.08vpp vp+ vp- njm5532 470p r1 4.7k 470p 4.7k when r1=200 fc=93.2khz, q=0.712, g=-0.1b at 40khz when r1=180 fc=98.2khz, q=0.681, g=-0.2db at 40khz 3900p 20 20 2200p a b figure 65. output buffer circuit example 1 (dc coupled differential output) figure 66 shows the output buffer circuit example 2. the output level of this circuit is 4.16vpp (ak4611: typ. 2.08vpp). 4.7k vp+ = +12v vp- = -12v r1 4.7k aout- ak4611 aout+ 4.16vpp analog out 2.08vpp 2.08vpp vp+ vp- njm5532 470p r1 4.7k 470p 4.7k when r1=180 fc=90.1khz, q=0.735, g=-0.04b at 40khz when r1=150 fc=99.0khz, q=0.680, g=-0.23db at 40khz 3900p 22 22 20 20 2200p a b figure 66. output buffer circuit example 2 (ac coupled differential output)
[ak4611] ms1050-e-02 2010/06 - 65 - figure 67 shows the output buffer circuit example 3. the output level of this circuit is 4.16vpp (ak4611: typ. 2.08vpp). 4.7k vp+ = +12v vp- = -12v aout- ak4611 aout+ analog out 2.08vpp 4.7k vp+ vp- njm5532 4.16vpp open 10k 22 470p 470p 4.7k 4.7k figure 67. output buffer circuit example 3 (ac coupled single-end output) figure 68 shows the output buffer circuit example 4. the output level of this circuit is 2.08vpp (ak4611: typ. 2.08vpp). aout- ak4611 aout+ analog out 2.08vpp 10k 22 2.08vpp open figure 68. output buffer circuit example 4 (ac coupled single-end output)
[ak4611] ms1050-e-02 2010/06 - 66 - package z 80-pin lqfp ( unit: mm ) 14.00.2 12.00.2 0.50 1 20 21 40 41 60 61 80 12.00.2 14.00.2 1.25typ 0.08 m 0.125 +0.10 -0.05 0.500.2 1.85max 0.10 +0.15 -0.10 1.400.2 0.10 0.200.1 0 ~ 10 package & lead frame material package molding compound: epoxy resin, halogen (bromine and chlorine) free lead frame material: cu lead frame surface treatment: solder (pb free) plate
[ak4611] ms1050-e-02 2010/06 - 67 - marking (ak4611eq) ak4611eq xxxxxxx 1) pin #1 indication 2) date code: xxxxxxx(7 digits) 3) marking code: ak4611eq 4) asahi kasei logo marking (AK4611VQ) AK4611VQ xxxxxxx 1) pin #1 indication 2) date code: xxxxxxx(7 digits) 3) marking code: AK4611VQ 4) asahi kasei logo
[ak4611] ms1050-e-02 2010/06 - 68 - revision history date (yy/mm/dd) revision reason page contents 09/02/06 00 first edition 09/06/05 01 specification change 10 analog characteristics adc analog input characteristics (differential) s/(n+d) fs=48khz, -1dbfs: 89 88 (min) 10/06/14 02 description addition ak4611eq was added. important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporatio n of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distri butes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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